This portal has been archived. Explore the next generation of this technology.
Device-aware inference operations in SONOS nonvolatile memory arrays
lib:c4bbd11b4c64ef46 (v1.0.0)
Authors: Christopher H. Bennett,T. Patrick Xiao,Ryan Dellana,Vineet Agrawal,Ben Feinberg,Venkatraman Prabhakar,Krishnaswamy Ramkumar,Long Hinh,Swatilekha Saha,Vijay Raghavan,Ramesh Chettuvetty,Sapan Agarwal,Matthew J. Marinella
ArXiv: 2004.00802
Document: PDF DOI
Abstract URL: https://arxiv.org/abs/2004.00802v1
Non-volatile memory arrays can deploy pre-trained neural network models for edge inference. However, these systems are affected by device-level noise and retention issues. Here, we examine damage caused by these effects, introduce a mitigation strategy, and demonstrate its use in fabricated array of SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) devices. On MNIST, fashion-MNIST, and CIFAR-10 tasks, our approach increases resilience to synaptic noise and drift. We also show strong performance can be realized with ADCs of 5-8 bits precision.
ArXiv: 2004.00802
Document: PDF DOI
Abstract URL: https://arxiv.org/abs/2004.00802v1
Non-volatile memory arrays can deploy pre-trained neural network models for edge inference. However, these systems are affected by device-level noise and retention issues. Here, we examine damage caused by these effects, introduce a mitigation strategy, and demonstrate its use in fabricated array of SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) devices. On MNIST, fashion-MNIST, and CIFAR-10 tasks, our approach increases resilience to synaptic noise and drift. We also show strong performance can be realized with ADCs of 5-8 bits precision.
Relevant initiatives
Related knowledge about this paper
Reproduced results (crowd-benchmarking and competitions)
Artifact and reproducibility checklists
- ACM/cTuning artifact appendix and reproducibility checklist
- NeurIPS reproducibility checklist
- SIGPLAN's checklist for empirical evaluation
- Collective Knowledge (organizing research projects based on FAIR principles)